vdd/vddq = 2.5 ~ 2.7v all inputs and outputs are compatible with sstl_2 interface fully differential clock inputs (ck, /ck) operation double data rate interface source synchronous - data transaction aligned to bidirectional data strobe (dqs) x16 device has two bytewide data strobes (udqs, ldqs) per each x8 i/o data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) on chip dll align dq and dqs transition with ck transition dm mask write data-in at the both rising and falling edges of the data strobe all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock cas latency 3 supported programmable burst length 2 / 4 / 8 with both sequential and interleave mode internal four bank operations with single pulsed /ras tras lock-out function supported auto refresh and self refresh supported 8192 refresh cycles / 64ms jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch